Jigas de teste em protótipos de circuito impresso: estudo de método e desenvolvimento de uma IDE

Abstract

This work presents a study on test jigs applied to printed circuit boards (PCBs) and proposes an integrated proof of concept aimed at facilitating and simplifying the development of test plans through an IDE. The focus is on PCBs with test points on their upper and/or lower surfaces. Test jigs are essential for the verification and validation of electronic circuits, ensuring that components function according to technical specifications. The developed IDE seeks to streamline circuit validation and program logic debugging by analyzing variations in digital signal levels at the PCB test points. Through the study of current solutions, the main functionalities and technical feasibility of the proposed solution are evaluated. The results demonstrate that the developed IDE has the potential to simplify the implementation of hardware tests on prototypes by adding a layer of abstraction between the physical jig and the logical jig, reducing its development time and standing out as a valuable complement to the hardware validation sector.